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[VHDL-FPGA-Verilog] crc8

Description: 8位crc的verilog设计 通过仿真综合验证并已应用在工程里面 -verilog of 8bit error checkout
Platform: | Size: 1024 | Author: yangyanwen | Hits:

[VHDL-FPGA-Verilog] Desktop

Description: crc校验码verilog代码，24bits，按原理写的代码-cyclic redundancy check 24 bits verilog
Platform: | Size: 1024 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] crc

Description: 用verilog实现串进并出的CRC算法-Achieved with verilog into and out of the CRC series algorithm
Platform: | Size: 1024 | Author: santa | Hits:

[VHDL-FPGA-Verilog] eth_crc

Description: crc校验码Verilog 程序。此为4位并行crc——32校验。-crc checksum Verilog program. This is a 4-bit parallel crc- 32 check.
Platform: | Size: 2048 | Author: hepeng | Hits:

[VHDL-FPGA-Verilog] crc

Description: 非常不错的CRC冗余纠错编码Verilog源码-非常不错的CRC编码Verilog源码
Platform: | Size: 1024 | Author: dsahd | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 各类CRC效验码 有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8-CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8
Platform: | Size: 6144 | Author: 吴伟珍 | Hits:

[VHDL-FPGA-Verilog] crc_eth

Description: Verilog code to add a CRC field at the end of an ethernet frame.
Platform: | Size: 2048 | Author: caracol | Hits:

[VHDL-FPGA-Verilog] HDLC

Description: verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
Platform: | Size: 69632 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] MACtop

Description: 基于FPGA的以太网控制器（MAC）源码，包括发送、接收、控制、CRC、寄存器、计数器等模块-Ethernet MAC sub-layer protocol
Platform: | Size: 128000 | Author: cmf | Hits:

[VHDL-FPGA-Verilog] crc_gen.pl

Description: CRC verilog 生成脚本，可自己设定CRC 参数-CRC verilog generate scripts, you can set their own parameters CRC
Platform: | Size: 3072 | Author: 沈磊 | Hits:

[VHDL-FPGA-Verilog] CRC-32

Description: 一个关于32位循环冗余校验的verilog代码-A 32-bit cyclic redundancy check on the verilog code
Platform: | Size: 2048 | Author: 袁桂毅 | Hits:

[VHDL-FPGA-Verilog] gen_crc

Description: 任意位宽，任意多项式，并行CRC生成verilog代码脚本-CRC verilog gen script, for any width of data input
Platform: | Size: 1024 | Author: wds | Hits:

[VHDL-FPGA-Verilog] crc

Description: crc校验模块verilog源代码，符合EPC C1G2协议-The agreement with EPC C1G2 digital baseband crc verify module source code
Platform: | Size: 2048 | Author: 黄巾 | Hits:

[Crack Hack] CRC

Description: CRC校验xilinx器件生成CRC校验verilog文件-CRC perl
Platform: | Size: 5120 | Author: icsong | Hits:

[Other] CRC-coding-decoder-design-Verilog

Description: 《CRC编码译码器的设计》，介绍了CRC循环校验等详细知识-CRC codec design, a detailed knowledge of the CRC check loop
Platform: | Size: 7859200 | Author: zhouqiang | Hits:

[VHDL-FPGA-Verilog] crc-16b-parallel

Description: CRC generator in verilog hdl
Platform: | Size: 1024 | Author: Srikanth | Hits:

[VHDL-FPGA-Verilog] CRC

Description: CRC校验参考设计Verilog代码,crc8,16,32bit- crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input.
Platform: | Size: 10240 | Author: guangngqiang | Hits:

[VHDL-FPGA-Verilog] CRC

Description: 用VERILOG语言实现的CRC循环冗余校验码，已成功用于实际项目。-With VERILOG language of the CRC cyclic redundancy check code has been successfully used for actual projects.
Platform: | Size: 484352 | Author: zyb | Hits:

[VHDL-FPGA-Verilog] CRC_test

Description: 基于verilog编写的CRC校验程序，采用LFSR电路实现。-CRC verilog
Platform: | Size: 20480 | Author: jack | Hits:

[Software Engineering] Verilog

Description: Verilog初学者使用，各种verilog的典型电路设计。包括状态机、CRC校验等。-Verilog beginners, abundant examples
Platform: | Size: 271360 | Author: 李茜 | Hits:
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